Decoder Hardware Architecture for HEVC
Name
hardware.pdf
Size
3.98 MB
Format
Adobe PDF
Checksum (MD5)
33348efb0e4d3e37b3bc491f1895e97d
Author(s)
Tikekar, Mehul
Huang, Chao-Tsung
Sze, Vivienne
Juvekar, Chiraag Shashikant
Chandrakasan, Anantha P.
Date Issued
2014
Journal
High Efficiency Video Coding (HEVC)
Publisher
Springer-Verlag
Citation
Tikekar, Mehul, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, and Anantha Chandrakasan. “Decoder Hardware Architecture for HEVC.” High Efficiency Video Coding (HEVC) (2014): 303–341.
Version
Author's final manuscript
Abstract
This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1007/978-3-319-06895-4_10
