ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
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Devadas-ARCc.pdf
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Author(s)
Khan, Omer
Hoffmann, Henry Christian
Lis, Mieszko
Hijaz, Farrukh
Agarwal, Anant
Devadas, Srinivas
Date Issued
October 2011
Journal
Proceedings of the IEEE International Conference on Computer Design, ICCD 2011
Publisher
Institute of Electrical and Electronics Engineers
Citation
Khan, Omer et al. “ARCc: A Case for an Architecturally Redundant Cache-coherence Architecture for Large Multicores.” IEEE, 2011. 411–418. Web.
Version
Author's final manuscript
Abstract
This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware and ARCc enables seamless transition between the two protocols. We present an online analytical model implemented in the hardware that predicts performance and triggers a transition between the two coherence protocols at application-level granularity. The ARCc architecture delivers up to 1.6× higher performance and up to 1.5× lower energy consumption compared to the directory-based counterpart. It does so by identifying applications which benefit from the large shared cache capacity of shared-NUCA because of lower off-chip accesses, or where remote-cache word accesses are efficient.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1109/ICCD.2011.6081431
