Dynamic Time Warping Constraints for Semiconductor Processing
Name
owens-rowens2-sm-eecs-2024-thesis.pdf
Description
Thesis PDF
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1.76 MB
Format
Adobe PDF
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6ea89bb4c76aeb5801d142a33808f276
Author(s)
Owens, Rachel
Advisor(s)
Boning, Duane S.
Date Issued
May 2024
Publisher
Massachusetts Institute of Technology
Abstract
Semiconductor manufacturing processes have become increasingly complex with the continued growth of chip manufacturing. Monitoring these processes for anomalies is crucial for maintaining quality and yield. However, a notable challenge for monitoring time series signals are the nonlinear variations in signal timing. These small, but acceptable, temporal variations are typically caused by small run-to-run differences that are inherent to the process. Dynamic time warping (DTW) can be used for temporal alignment of signals, but is computationally expensive and prone to errors.
In this thesis, a new method is presented for preprocessing semiconductor fabrication sensor signals that improves anomaly detection model performance. The new method uses domain knowledge – specifically, process recipe step numbers – to create constraints that better align signals along the time dimension, that addresses this problem of nonlinear signal alignment. These constraints are tested on both synthetic as well as industrial datasets. The new step-constrained DTW is also extended as a distance measure for clustering time series.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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