Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion
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3695053.3731037.pdf
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2.46 MB
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Author(s)
Nasr-Esfahany, Arash
Alizadeh, Mohammad
Lee, Victor
Alam, Hanna
Coon, Brett
Culler, David
Dadu, Vidushi
Dixon, Martin
Levy, Henry
Pandey, Santosh
Date Issued
June 20, 2025
Publisher
ACM|Proceedings of the 52nd Annual International Symposium on Computer Architecture
Citation
Arash Nasr-Esfahany, Mohammad Alizadeh, Victor Lee, Hanna Alam, Brett W. Coon, David Culler, Vidushi Dadu, Martin Dixon, Henry M. Levy, Santosh Pandey, Parthasarathy Ranganathan, and Amir Yazdanbakhsh. 2025. Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion. In Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA '25). Association for Computing Machinery, New York, NY, USA, 1480–1494.
Version
Final published version
Abstract
Cycle-level simulators such as gem5 are widely used in microarchitecture design, but they are prohibitively slow for large-scale design space explorations. We present Concorde, a new methodology for learning fast and accurate performance models of microarchitectures. Unlike existing simulators and learning approaches that emulate each instruction, Concorde predicts the behavior of a program based on compact performance distributions that capture the impact of different microarchitectural components. It derives these performance distributions using simple analytical models that estimate bounds on performance induced by each microarchitectural component, providing a simple yet rich representation of a program’s performance characteristics across a large space of microarchitectural parameters. Experiments show that Concorde is more than five orders of magnitude faster than a reference cycle-level simulator, with about 2% average Cycles-Per-Instruction (CPI) prediction error across a range of SPEC, open-source, and proprietary benchmarks. This enables rapid design-space exploration and performance sensitivity analyses that are currently infeasible, e.g., in about an hour, we conducted a first-of-its-kind fine-grained performance attribution to different microarchitectural components across a diverse set of programs, requiring nearly 150 million CPI evaluations.
Description
ISCA ’25, Tokyo, Japan
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution
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DOI of Published Version
https://doi.org/10.1145/3695053.3731037
