Simulation and Design of Quantum Processors for Low‑Overhead Quantum Error Correction
Name
pahl-david721-sm-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
67.9 MB
Format
Adobe PDF
Checksum (MD5)
6d55386d8572a92e45d0f62d2da35e89
Author(s)
Pahl, David
Advisor(s)
Oliver, William D.
Grover, Jeffrey A.
Date Issued
May 2025
Publisher
Massachusetts Institute of Technology
Abstract
This thesis investigates the simulation and design of the hardware architecture required for large‑scale quantum error correction (QEC). Specifically, we design microwave circuits for fast and high‑fidelity readout and devise a long‑range coupler (LRC) that spans five qubit lattice sites, suitable for low‑overhead quantum low‑density parity‑check (qLDPC) codes [1]. We present a prototypical nine‑qubit qLDPC code incorporating two long‑ range couplers and optimized readout circuits, achieving state‑of‑the‑art readout fidelities of up to 99.63% in 56 ns and demonstrating strong, well‑targeted couplings mediated by the LRC. Our simulations employ an efficient microwave abstraction based on ABCD transfer matrices, modeling complete qubit devices as networks of circuit elements. We use this formalism to develop a closed‑loop optimization algorithm that determines optimal readout parameters in seconds. The ABCD framework also accurately captures the multi‑mode behavior of the LRC, offering a valuable tool for developing large‑scale, low‑ overhead QEC devices.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
In Copyright - Educational Use Permitted
Copyright retained by author(s)
Persistent DSpace Link
