Making Concurrent Hardware Verification Sequential
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Author(s)
Bourgeat, Thomas
Liu, Jiazheng
Chlipala, Adam
Arvind
Date Issued
June 13, 2025
Journal
Proceedings of the ACM on Programming Languages
Publisher
ACM
Citation
Thomas Bourgeat, Jiazheng Liu, Adam Chlipala, and Arvind. 2025. Making Concurrent Hardware Verification Sequential. Proc. ACM Program. Lang. 9, PLDI, Article 228 (June 2025), 25 pages.
Version
Final published version
Abstract
Compared to familiar hardware-description languages like Verilog, rule-based languages like Bluespec offer
opportunities to import modularity features from software programming. While Verilog modules are about
connecting wires between submodules, Bluespec modules resemble objects in object-oriented programming,
where interactions with a module occur only through calls to its methods. However, while software objects
can typically be characterized one method at a time, the concurrent nature of hardware makes it essential to
consider the repercussions of invoking multiple methods simultaneously. Prior formalizations of rule-based
languages conceptualized modules by describing their semantics considering arbitrary sets of simultaneous
method calls. This internalized concurrency significantly complicates correctness proofs. Rather than analyzing
methods one-at-a-time, as is done when verifying software object methods, validating the correctness of
rule-based modules necessitated simultaneous consideration of arbitrary subsets of method calls. The result
was a number of proof cases that grew exponentially in the size of the module’s API.
In this work, we side-step the exponential blowup through a set of judicious language restrictions. We
introduce a new Bluespec-inspired formal language, Fjfj, that supports sequential characterization of modules,
while preserving the concurrent hardware nature of the language. We evaluated Fjfj by implementing it in
Coq, proving the key framework principle: the refinement theorem. We demonstrated Fjfj’s expressivity via
implementation and verification of three examples: a pipelined processor, a parameterized crossbar, and a
network switch.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1145/3729331
