Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate
Name
62413893-MIT.pdf
Description
Full printable version
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2.56 MB
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Checksum (MD5)
85fd59a04e43797a6ef0ca13165487c4
Author(s)
Selbst, Andrew D. (Andrew David)
Advisor(s)
Rahul Sarpeshkar.
Date Issued
2005
Publisher
Massachusetts Institute of Technology
Abstract
Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 63).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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