Throughput analysis of input-queued packet switches : multicasting and speedup
Name
42306218-MIT.pdf
Description
Full printable version
Size
3.84 MB
Format
Adobe PDF
Checksum (MD5)
8d8332a1e6ef5c735963c400c4ac0482
Author(s)
Maruta, Toru, 1967-
Advisor(s)
Balaji Prabhakar.
Date Issued
1998
Publisher
Massachusetts Institute of Technology
Abstract
The widespread use of new applications such as voice/video streaming, the WWW, and the MBone has caused an increased demand for bandwidth in the Internet. In response to this, Internet backbone speeds have increased to several gigabits/sec, thus causing packet switches and routers to become potential bottlenecks of the network. There is also an increasing need to support services with different QoS requirements over a single integrated network. The support of such capabilities will require an even higher performance of packet switches and routers. Among several competing high-speed router architectures, those based on a crossbar backplane have become the most widely used by the industry. Essentially, crossbar architectures come in two flavors: (1) The Output-queued Architecture, and (2) The Input-queued Architecture. Despite superior throughput and delay performance, the output-queued architecture is severely impacted by memory bandwidth constraints at high speeds. On the other hand, input-queued switches/routers do not suffer from this, but deliver a poor throughput and delay performance due to the so-called Head of Line (HOL) blocking problem. Therefore, a number of recent studies have focused on overcoming the limitations of input-queued switches through the use of "speedup" and clever packet scheduling algorithms. Research on designing efficient switches for multicast traffic is also of great interest currently, since multicast traffic is a growing proportion of Internet traffic. In this thesis, we revisit the analysis of input-queued switches. Our contribution consists of the use of a conceptual combinatorial model of "balls and urns" to formulate and analyze the behavior of input-queued switches both with and without speedup. We also analyze the throughput performance of multicast switches when the fanout is deterministic, and obtain precise analytical results which exactly match simulations. Finally we analyze the throughput of multicast switches when the fanout is random and find, somewhat surprisingly, that the throughput is lowest when the fanout is deterministic.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (p. 75-76).
Subjects
Electrical Engineering and Computer Science
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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