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  5. Floating point multiply/add unit for the M-machine node processor

Floating point multiply/add unit for the M-machine node processor

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Author(s)
Hartman, Daniel K
Advisor(s)
Wililam J. Dally.
Date Issued
1996
Publisher
Massachusetts Institute of Technology
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
Includes bibliographical references (p. 177).
Subjects
Electrical Engineering and Computer Science
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/38791
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