The Clock Distribution Systems of the Multiprocessor Emulation Facility
Name
MIT-LCS-TR-366.pdf
Size
3.39 MB
Format
Adobe PDF
Checksum (MD5)
ca72ef9fad2f567869db14791806d8a6
Author(s)
Younis, Saed G.
Advisor(s)
Arvind
Date Issued
June 1986
Series/Report no.
MIT-LCS-TR-366
Abstract
Consisting of 32 high-speed processors, the multiple processor emulation facility communicates data between its processors through the use of synchronous, high-bandwidth packet switches residing on the ports of every processor. Because of the synchronous nature of these packet switches, there was a need to design a clock distribution system that can distribute a clock signal to the 32 ports with as little clock skew as possible.
Persistent DSpace Link
