Cell-based array for deep sub-micron technologies
Name
57241123-MIT.pdf
Description
Full printable version
Size
9.21 MB
Format
Adobe PDF
Checksum (MD5)
e84b84cf92985d7886ea9a86e2d5d39b
Author(s)
Oey, James Boe-Kian, 1980-
Advisor(s)
Christopher J. Terman.
Date Issued
2003
Publisher
Massachusetts Institute of Technology
Abstract
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 161).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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