APRIL: A Processor Architecture for Multiprocessing
Name
MIT-LCS-TM-450.pdf
Size
998.81 KB
Format
Adobe PDF
Checksum (MD5)
af3988f4e1db34dbb4399e7001a6c2da
Author(s)
Agarwal, Anant
Lim, Beng-Hong
Kranz, David
Kubiatowicz, John
Date Issued
1991
Series/Report no.
MIT-LCS-TM-450
Abstract
Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. We show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles.
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