Modeling of planarization technologies
Name
192003972-MIT.pdf
Description
Full printable version
Size
18.59 MB
Format
Adobe PDF
Checksum (MD5)
92b85691cdbba1a2778c4c4ff732bbf5
Author(s)
Truque, Daniel
Advisor(s)
Duane S. Boning.
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
The need for better planarity becomes more critical in semiconductor manufacturing as dimensions and tolerance margins keep shrinking. The purpose of this thesis is to understand and model new technologies for the planarization of integrated circuits. Two technologies and models are explored: characterization and modeling of a novel polishing pad, and a dynamic wafer level physical model for electrochemical-mechanical polishing (ECMP). The novel pad contains water soluble particles that dissolve in the slurry when they reach the surface. Different pads, with varying particle concentrations and sizes, are tested by polishing test wafers to extract the necessary model parameters to model each pad's polishing performance. The effect on chip uniformity and step height planarization are studied. The simulations and analysis enable understanding and comparison of pad design decisions, to achieve the best tradeoff in the performance metrics considered. In the second planarization technology, wafer scale uniformity effects are studied in an emerging copper polishing alternative, ECMP. The proposed dynamic wafer level physical ECMP model is able to capture the physics behind the ECMP process, based on modeling of electrical current flowing through the copper thin film on the wafer surface and the ECMP electrolyte solution. The model is able to fit zonal relative removal rates with root mean square error less than 7%, compared to existing empirical models and experiments.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2007.
"May 24, 2007."
Includes bibliographical references (p. 81-83).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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