A Framework for Solving VSLI Graph Layout Problems
Name
MIT-LCS-TR-305.pdf
Size
2.19 MB
Format
Adobe PDF
Checksum (MD5)
6de8be4ccfc027b0e9ab647e3af4527c
Author(s)
Bhatt, Sandeep N.
Leighton, Frank Thomson
Date Issued
October 1983
Series/Report no.
MIT-LCS-TR-305
Abstract
This paper introduces a new divide-and-conquer framework for VLSI graph layout. Universally close upper and lower bounds are obtained for important cost functions such as layout area and propagation delay. The framework is also effectively used to design regular and configuration layouts, to assemble large networks of processors using restructurable chips, and to configure networks around faulty processors. it is also shown how good graph partitioning heuristics may be used to develop a provably good layout strategy.
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