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Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications

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Author(s)
Chu, Tam-Anh
Advisor(s)
Dennis, Jack B.
Date Issued
June 1987
Series/Report no.
MIT-LCS-TR-393
Abstract
This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs). Control circuits synthesized from this graph model are speed-independent and capable of performing concurrent operation.
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