ARES: Adaptive, Reconfigurable, Erasure Coded, Atomic Storage
Author(s)
Nicolaou, Nicolas
Cadambe, Viveck
Prakash, N.
Konwar, Kishori
Medard, Muriel
Lynch, Nancy A.
Date Issued
October 2019
Journal
Proceedings - International Conference on Distributed Computing Systems
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Nicolaou, Nicolas, Cadambe, Viveck, Prakash, N, Konwar, Kishori, Medard, Muriel et al. 2019. "ARES: Adaptive, Reconfigurable, Erasure Coded, Atomic Storage." Proceedings - International Conference on Distributed Computing Systems, 2019-July.
Version
Final published version
Abstract
© 2019 IEEE. Emulating a shared atomic, read/write storage system is a fundamental problem in distributed computing. Replicating atomic objects among a set of data hosts was the norm for traditional implementations (e.g., [6]) in order to guarantee the availability and accessibility of the data despite host failures. As replication is highly storage demanding, recent approaches suggested the use of erasure-codes to offer the same fault-tolerance while optimizing storage usage at the hosts. Initial works focused on a fix set of data hosts. To guarantee longevity and scalability, a storage service should be able to dynamically mask hosts failures by allowing new hosts to join, and failed host to be removed without service interruptions. This work presents the first erasure-code based atomic algorithm, called ARES, which allows the set of hosts to be modified in the course of an execution. ARES is composed of three main components: (i) a reconfiguration protocol, (ii) a read/write protocol, and (iii) a set of data access primitives. The design of ARES is modular and is such to accommodate the usage of various erasure-code parameters on a per-configuration basis. We provide bounds on the latency of read/write operations and analyze the storage and communication costs of the ARES algorithm.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Research Laboratory of Electronics
Terms of Use
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Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/icdcs.2019.00216
