A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 mu m CMOS
Name
Park-2009-A 78 dB SNDR 87 mW 2.pdf
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3.2 MB
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Checksum (MD5)
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Author(s)
Park, Matthew
Perrott, Michael H.
Date Issued
December 2009
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Park, M., and M.H. Perrott. “A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time \Delta \Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 \mu m CMOS.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3344-3358. © 2009 Institute of Electrical and Electronics Engineers.
Version
Final published version
Abstract
The use of a VCO-based integrator and quantizer within a continuous-time (CT) \Delta \Sigma analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 \mum CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm[superscript 2] demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/jssc.2009.2032703
