Exploiting semantic commutativity in hardware speculation
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Sanchez_Exploiting Semantic.pdf
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Author(s)
Zhang, Guowei
Chiu, Virginia
Sanchez, Daniel
Date Issued
December 2016
Journal
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Zhang, Guowei et al. “Exploiting Semantic Commutativity in Hardware Speculation.” 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 15-19 2016, Taipei,Taiwan, Institute of Electrical and Electronics Engineers (IEEE), December 2016 © 2016 Institute of Electrical and Electronics Engineers (IEEE)
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Author's final manuscript
Abstract
Hardware speculative execution schemes such as hardware transactional memory (HTM) enjoy low run-time overheads but suffer from limited concurrency because they rely on reads and writes to detect conflicts. By contrast, software speculation schemes can exploit semantic knowledge of concurrent operations to reduce conflicts. In particular, they often exploit that many operations on shared data, like insertions into sets, are semantically commutative: they produce semantically equivalent results when reordered. However, software techniques often incur unacceptable run-time overheads. To solve this dichotomy, we present COMMTM, an HTM that exploits semantic commutativity. CommTM extends the coherence protocol and conflict detection scheme to support user-defined commutative operations. Multiple cores can perform commutative operations to the same data concurrently and without conflicts. CommTM preserves transactional guarantees and can be applied to arbitrary HTMs. CommTM scales on many operations that serialize in conventional HTMs, like set insertions, reference counting, and top-K insertions, and retains the low overhead of HTMs. As a result, at 128 cores, CommTM outperforms a conventional eager-lazy HTM by up to 3.4 χ and reduces or eliminates aborts.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/MICRO.2016.7783737
