Photonic Device Layout Within the Foundry CMOS Design Environment
Name
Orcutt-2010-Photonic Device Layout Within the Foundry CMOS Design Environment.pdf
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583.32 KB
Format
Adobe PDF
Checksum (MD5)
16d83b6520a3b50d36d5abc56280e807
Author(s)
Orcutt, Jason Scott
Ram, Rajeev J.
Date Issued
March 2010
Journal
IEEE Photonics Technology Letters
Publisher
Institute of Electrical and Electronics Engineers
Citation
Orcutt, J.S., and R.J. Ram. “Photonic Device Layout Within the Foundry CMOS Design Environment.” Photonics Technology Letters, IEEE 22.8 (2010): 544-546. © Copyright 2010 IEEE
Version
Final published version
Abstract
A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Research Laboratory of Electronics
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/lpt.2010.2041445
