Optimization of Integrated Transistors for Very High Frequency DC-DC Converters
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Perreault_Optimization-of-Integrated.pdf
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2.25 MB
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Author(s)
Sagneri, Anthony D.
Anderson, David I.
Perreault, David J.
Date Issued
July 2013
Journal
IEEE Transactions on Power Electronics
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Sagneri, Anthony D., David I. Anderson, and David J. Perreault. “Optimization of Integrated Transistors for Very High Frequency DC-DC Converters.” IEEE Trans. Power Electron. 28, no. 7 (July 2013): 3614–3626.
Version
Author's final manuscript
Abstract
This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout versus loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50-MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3-μm gate length in 20-V design rules is validated at 35 V, offering reduced parasitic resistance and capacitance, as compared to the 5.5-μm device. Compared to the original design, loss is up to 75% lower in the example application.
MIT Department
Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems
Massachusetts Institute of Technology. School of Engineering
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/TPEL.2012.2222048
