Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration
Name
Yang-2009-Thermal considerations for advanced SOI substrates designed for III-VSi heterointegration.pdf
Size
358.63 KB
Format
Adobe PDF
Checksum (MD5)
1ab89bce82bba085a6b7f80b4e08a22f
Author(s)
Bulsara, Mayank
Fitzgerald, Eugene A.
Yang, N.
Liu, W. K.
Lubyshev, D.
Fastenau, J. M.
Wu, Y.
Urteaga, M.
Ha, W.
Bergman, J.
Date Issued
October 2009
Journal
IEEE International SOI Conference, 2009
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Yang, N. et al. “Thermal Considerations for Advanced SOI Substrates Designed for III-V/Si Heterointegration.” IEEE, 2009. 1–2. © 2009 IEEE.
Version
Final published version
Abstract
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications.
MIT Department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/SOI.2009.5318745
