LEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic [Extended Version]
Name
MIT-CSAIL-TR-2010-054.pdf
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447.09 KB
Format
Adobe PDF
Checksum (MD5)
57db6d1f9acebacf3341b5132c3b8b1c
Author(s)
Adler, Michael
Fleming, Kermin E.
Parashar, Angshuman
Pellauer, Michael
Emer, Joel
Advisor(s)
Arvind
Date Issued
November 23, 2010
Series/Report no.
MIT-CSAIL-TR-2010-054
Abstract
Developers accelerating applications on FPGAs or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions. LEAP scratchpads for reconfigurable logic dynamically allocate and manage multiple, independent, memory arrays in a large backing store. Scratchpad accesses are cached automatically in multiple levels, ranging from shared on-board, RAM-based, set-associative caches to private caches stored in FPGA RAM blocks. In the LEAP framework, scratchpads share the same interface as on-die RAM blocks and are plug-in replacements. Additional libraries support heap management within a storage set. Like software developers, accelerator authors using scratchpads may focus more on core algorithms and less on memory management. Two uses of FPGA scratchpads are analyzed: buffer management in an H.264 decoder and memory management within a processor microarchitecture timing model.
Description
CORRECTION: The authors for entry [4] in the references should have been "E. S. Chung,
J. C. Hoe, and K. Mai".
Subjects
FPGA
memory management
caches
Terms of Use
Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported
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