Design-technology Co-optimization for Sub-2 nm Technology Node Based on 2D Materials
Name
yao-aijia-sm-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
6.66 MB
Format
Adobe PDF
Checksum (MD5)
06b210e62650f44e585e6c44b41c621c
Author(s)
Yao, Aijia
Advisor(s)
Palacios, Tomás
Date Issued
February 2025
Publisher
Massachusetts Institute of Technology
Abstract
Emerging disruptive technologies such as Artificial Intelligence (AI) and 6G communications have driven stringent demands for hardware components that enable faster and more energy-efficient computation. With the diminishing returns of traditional silicon-based scaling and the escalating complexity of advanced semiconductor processes, two-dimensional (2D) materials offer promising opportunities when developed through Design-Technology Co-Optimization (DTCO). This thesis presents a comprehensive study of DTCO with a novel framework tailored for 2D material-based electronics that addresses critical challenges in material synthesis, device design, and circuit integration. In this framework, experimental material and device data are integrated into the design and optimization of MoS₂-based multichannel transistors (MCTs). With the help of DTCO, we have achieved record performance for double-gate, single-channel MoS₂ transistors as well as the first demonstration of high-performance, functional double channel MoS₂ transistors. Based on the results of MCTs, a Process Design Kit (PDK) is developed to facilitate circuit-level integration. These advancements constitute a promising foundation for the development of next-generation electronics beyond sub-2 nm technology node.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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