Performance Analysis of the Apple AMX Matrix Accelerator
Name
zhou-jzhou08-meng-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
1.74 MB
Format
Adobe PDF
Checksum (MD5)
0503590e9bb28156d3e3997347e44bed
Author(s)
Zhou, Jonathan
Advisor(s)
Amarasinghe, Saman
Date Issued
September 2025
Publisher
Massachusetts Institute of Technology
Abstract
Apple Silicon integrates a dedicated Apple Matrix Coprocessor (AMX) that executes outer-product style computations with high throughput, but its public programming model remains largely hidden behind the Accelerate framework. This thesis turns AMX into a more predictable and practical target by combining (i) empirical throughput characterization, (ii) a case study on AMX specific matrix multiplication (GEMM) design, and (iii) an interpretable rule-based latency model that predicts cycle counts for short AMX instruction sequences. First, microbenchmarks quantify AMX load/store and compute limits across matrix and vector modes and data types. We analyze throughput in both GFLOPS and AMX instructions per cycle, and also observe output register based throughput limitations. Second, we develop an in-place GEMM that uses masked outer products and strategically overlapping tiles to avoid scratch buffers used by Accelerate, outperforming Accelerate while preserving simplicity. Third, we introduce a compact latency model that decomposes cycles into per-instruction BaseTime, symmetric SwitchLatency for instruction changes, and instruction FullLatency (data dependency) terms. Fitted with non-negative coordinate descent on length-2 loops and validated on length-3 sequences via a lightweight loop simulation, the model obtains reasonably high accuracy while remaining helpful for those trying to understand the architecture.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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