A general technique for deterministic model-cycle-level debugging
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Author(s)
Khan, Asif Imtiaz
Vijayaraghavan, Muralidaran
Mithal, Arvind
Date Issued
July 2012
Journal
Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Khan, Asif, Muralidaran Vijayaraghavan, and Mithal Arvind. “A General Technique for Deterministic Model-Cycle-Level Debugging.” Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012) (July 2012).
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Author's final manuscript
Abstract
Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1109/MEMCOD.2012.6292307
