Hardware implementation of the Advanced Encryption Standard
Name
54040069-MIT.pdf
Description
Full printable version
Size
3.39 MB
Format
Adobe PDF
Checksum (MD5)
f973d4842a9b9f279bf1ab13e15b64e2
Author(s)
Maurer, Jennifer (Jennifer Robin), 1979-
Advisor(s)
Jonathan H. Raymond and Donald E. Troxel.
Alternative Title
Hardware implementation of the AES
Date Issued
2003
Publisher
Massachusetts Institute of Technology
Abstract
This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. The work described in the paper was completed as a part of MIT's VI-A program in the ASIC Digital Cores III group of the Microelectronics Division at IBM.
Description
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (leaves 97-98).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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