A Logic Design for the Cell Block of a Data-flow Processor
Name
MIT-LCS-TM-093.pdf
Size
24.84 MB
Format
Adobe PDF
Checksum (MD5)
8e4130f972518db53bdc21e3f893dec5
Author(s)
Amikura, Katsuhiko
Advisor(s)
Dennis, Jack B.
Date Issued
December 1977
Series/Report no.
MIT-LCS-TM-093
Abstract
Recently studies on parallel computation architecture have yielded a new type of computer architecture known as the data-flow processor. As part of the effort in realizing the data-flow processor, a logic design for the Cell Block of the basic data-flow processor is proposed in this thesis. The resulting design has a modular structure which is derived from a top-down decomposition of the specification given in an Aechitecutere Description Language. The desired speed of operation of the Cell Block is obtained by exploiting the parallellism inherent in its operation. The logic design is carried out using electronic devices available commerically today, but is based on an aynchronous communciation protocol.
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