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Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits
Name
1907.12882.pdf
Description
Submitted version
Size
1.94 MB
Format
Adobe PDF
Checksum (MD5)
205b5071ca973b7967077b9302db45fe
Date Issued
December 2019
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
2019. "Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December.
Version
Original manuscript
Abstract
© 2019 IEEE. As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
10.1109/IEDM19573.2019.8993515
