Ion traps fabricated in a CMOS foundry
Name
Chuang_Ion traps.pdf
Size
511.18 KB
Format
Adobe PDF
Checksum (MD5)
ec588e18052689b4fc959b10683e0d3e
Author(s)
Mehta, Karan Kartik
Bruzewicz, Colin D.
Sage, Jeremy M.
Chiaverini, John
Eltony, Amira
Chuang, Isaac L.
Ram, Rajeev J
Date Issued
July 2014
Journal
Applied Physics Letters
Publisher
American Institute of Physics (AIP)
Citation
Mehta, K. K., A. M. Eltony, C. D. Bruzewicz, I. L. Chuang, R. J. Ram, J. M. Sage, and J. Chiaverini. “Ion Traps Fabricated in a CMOS Foundry.” Applied Physics Letters 105, no. 4 (July 28, 2014): 044103.
Version
Original manuscript
Abstract
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.
MIT Department
Lincoln Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Department of Physics
Massachusetts Institute of Technology. Research Laboratory of Electronics
MIT-Harvard Center for Ultracold Atoms
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1063/1.4892061
