Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
Name
elsabbagh-farese-sm-eecs-2023-thesis.pdf
Description
Thesis PDF
Size
1.61 MB
Format
Adobe PDF
Checksum (MD5)
11391e5afd6547517846c64b0493d197
Author(s)
Elsabbagh, Fares
Advisor(s)
Sanchez, Daniel
Emer, Joel
Date Issued
June 2023
Publisher
Massachusetts Institute of Technology
Abstract
Fast simulation of digital circuits is crucial to build modern chips. Current processors and SoCs integrate hundreds of complex components, including cores, accelerators, and memory hierarchies. Simulating these systems is necessary to verify correctness and explore the design space. Simulation can happen at different levels of abstraction. In this work we focus on Register-Transfer-Level (RTL) simulation. While RTL simulators are frequently used in development due to their quick compilation times, their runtime performance is slow. This is because as the designs are scaled up, multicore communication and scheduling overheads limit performance and scalability.
We present ASH, a parallel architecture tailored to RTL simulation workloads. ASH consists of a tightly codesigned hardware architecture and compiler for RTL simulation. ASH exploits two key opportunities. First, it performs dataflow execution of small tasks to leverage the fine-grained parallelism in simulation workloads. Second, it performs selective event-driven execution to run only the fraction of the design exercised each cycle, skipping ineffectual tasks. ASH hardware provides a novel combination of dataflow and speculative execution, and ASH’s compiler features several novel techniques to automatically leverage this hardware.
We evaluate ASH in simulation using large Verilog designs that represent different types of architectures. With 256 simple cores, ASH is gmean 1,485× faster than 1-core Verilator, and it is 32× faster than Verilator on a server CPU with 32 complex cores while using 3× less area.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
In Copyright - Educational Use Permitted
Copyright retained by author(s)
Persistent DSpace Link
