Analysis of Mo sidewall ohmic contacts to InGaAs fins
Name
986497820-MIT.pdf
Description
Full printable version
Size
8.98 MB
Format
Adobe PDF
Checksum (MD5)
d7569f735481bf8d8431b4630fe82314
Author(s)
Choi, Dongsung
Advisor(s)
Jesús A. del Alamo.
Date Issued
2017
Publisher
Massachusetts Institute of Technology
Abstract
As transistor size is scaled down, the performance is degraded and many problems, so called shortchannel effects, arise. To address this problem, a vertical transistor structure such as vertical nanowire is suggested. In a vertical nanowire field-effect-transistor, the Ohmic contact at the top of the nanowire not only covers the top surface, but also wraps around the sidewall. Because the sidewall is considered to be different from the top surface, it is necessary to study the sidewall Ohmic contact properties such as the contact resistivity. In this thesis, to explore sidewall contact resistivity, a theoretical model for sidewall contacts is developed. For the suggested test structure, the fin sidewall contact (FSWC) structure, the sidewall contact is modeled with a transmission line model (TLM), and by using TLM, the sidewall contact resistance is derived. Also, an extraction method of the sidewall contact resistivity from the total resistance measured in FSWC structure is developed. Next, process steps to fabricate FSWC structure are developed. FSWC structure is made for Mo/n+-InGaAs contacts. The key step is that the fin etch mask on top of InGaAs is not removed and the metal (Mo) is sputtered so that InGaAs is contacted by the Mo only through the sidewall. Therefore, only a sidewall contact is made without a top contact. Also, to investigate the way to improve the sidewall contact resistivity, the effect of digital etch and annealing on the sidewall contact resistivity is explored. With the measured total resistance in FSWC structure and the extraction method for sidewall contact resistivity, sidewall contact resistivity for each split of digital etch and annealing are extracted. As a summary of the effect of digital etch and annealing, two cycles of digital etch or sequential annealing up to 400 °C improves the sidewall contact resistivity with little sacrifice in semiconductor resistivity. The best result of sidewall contact resistivity is 3.7±0.01[Omega] x [mu]m2 at 400 °C annealing, which is about 1.9 times improvement over the non-annealed value, 6.9±0.05 [Omega] x [mu]m2 but still about 5.4 times larger than the reported top contact resistivity of 0.69±0.3 [Omega] x [mu]m2.
Description
Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 79-80).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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