BUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS WITH MONOLITHIC CMOS SILICON PHOTONICS
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Batten_Building-Many-Core.pdf
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1.49 MB
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Adobe PDF
Checksum (MD5)
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Author(s)
Batten, Christopher
Joshi, Ajay J.
Orcutt, Jason Scott
Khilo, Anatol M.
Moss, Benjamin Roy
Holzwarth, Charles W.
Popovic, Milos
Li, Hanqing
Smith, Henry Ignatius
Hoyt, Judy L.
Date Issued
July 2009
Journal
IEEE Micro
Publisher
Institute of Electrical and Electronics Engineers
Citation
Christopher Batten, Ajay Joshi, Jason Orcutt, Anatol Khilo, Benjamin Moss, Charles W. Holzwarth, Miloš A. Popović, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanović, Krste Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics," IEEE Micro, vol. 29, no. 4, pp. 8-21, July/Aug. 2009, doi:10.1109/MM.2009.60 © 2009 IEEE
Version
Final published version
Abstract
Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://doi.ieeecomputersociety.org/10.1109/MM.2009.60
