Programmable Packet Scheduling at Line Rate
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Programmable packet.pdf
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Author(s)
McKeown, Nick
Chole, Sharad
Chuang, Shang-Tse
Agrawal, Anurag
Edsall, Tom
Sivaraman Kaushalram, Anirudh
Subramanian, Suvinay
Alizadeh Attar, Mohammadreza
Balakrishnan, Hari
Katti, Sachin Rajsekhar
Date Issued
August 2016
Journal
Proceedings of the 2016 conference on ACM SIGCOMM 2016 Conference - SIGCOMM '16
Publisher
Association for Computing Machinery
Citation
Sivaraman, Anirudh, Nick McKeown, Suvinay Subramanian, Mohammad Alizadeh, Sharad Chole, Shang-Tse Chuang, Anurag Agrawal, Hari Balakrishnan, Tom Edsall, and Sachin Katti. “Programmable Packet Scheduling at Line Rate.” Proceedings of the 2016 Conference on ACM SIGCOMM 2016 Conference - SIGCOMM ’16 (2016).
Version
Author's final manuscript
Abstract
Switches today provide a small menu of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a {\em programmable} packet scheduler, which allows scheduling algorithms---potentially algorithms that are unknown today---to be programmed into a switch without requiring hardware redesign. Our design uses the property that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, we observe that in many scheduling algorithms, definitive decisions on these two questions can be made when packets are enqueued. We use these observations to build a programmable scheduler using a single abstraction: the push-in first-out queue (PIFO), a priority queue that maintains the scheduling order or time. We show that a PIFO-based scheduler lets us program a wide variety of scheduling algorithms. We present a hardware design for this scheduler for a 64-port 10 Gbit/s shared-memory (output-queued) switch. Our design costs an additional 4% in chip area. In return, it lets us program many sophisticated algorithms, such as a 5-level hierarchical scheduler with programmable decisions at each level.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/2934872.2934899
