Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning
Name
final_version_asscc19.pdf
Size
4.65 MB
Format
Adobe PDF
Checksum (MD5)
7840e1a1ff10a1294e9a4976498761ec
Author(s)
Wang, Miaorong
Chandrakasan, Anantha P
Date Issued
April 2020
Journal
IEEE Asian Solid-State Circuits Conference (A-SSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Wang, Miaorong and Anantha P. Chandrakasan. "Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning." IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2019, Macau, Macao, Institute of Electrical and Electronics Engineers (IEEE), April 2020
Version
Author's final manuscript
Abstract
To support various edge applications, a neural network accelerator needs to achieve high flexibility and classification accuracy within a limited power budget. This paper proposes a weight tuning algorithm to improve the energy efficiency by lowering the switching activity. A flexible and runtime-reconfigurable CNN accelerator is co-designed with the algorithm and demonstrated with a feature extraction processor on an FPGA. The system is fully self-contained for small CNNs and speech keyword spotting is shown as an example. A fully integrated custom ASIC is also being fabricated for this system. Based on post place-and-route simulation of the ASIC, the weight tuning algorithm reduces the energy consumption of weight delivery and computation by 1.70x and 1.20x respectively with little loss in accuracy.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/a-sscc47793.2019.9056941
