Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access
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Sinangil_JSSC_paper_2014.pdf
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2.23 MB
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Adobe PDF
Checksum (MD5)
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Author(s)
Sinangil, Mahmut E.
Chandrakasan, Anantha P.
Date Issued
September 2013
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Sinangil, Mahmut E., and Anantha P. Chandrakasan. “Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access.” IEEE Journal of Solid-State Circuits 49, no. 1 (January 2014): 107–117.
Version
Author's final manuscript
Abstract
This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9 × lower energy/access when compared with an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/JSSC.2013.2280310
