A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems
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MQNV_ISSCC2013_upldSiteProof.pdf
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1.96 MB
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Author(s)
Qazi, Masood
Chandrakasan, Anantha P.
Amerasekera, Ajith
Date Issued
February 2013
Journal
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Qazi, M., A. Amerasekera, and A. P. Chandrakasan. “A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS for Nonvolatile Processing in Digital Systems.” 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (February 2013).
Version
Author's final manuscript
Abstract
Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance systems managing power by operating “normally off”. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/ISSCC.2013.6487695
