Nanostructured GaN transistors
Name
Nanostructured_GaN_Transistor2.pdf
Description
Accepted version
Size
315.12 KB
Format
Adobe PDF
Checksum (MD5)
bc333734cbd89037209d0519dc8d2a09
Author(s)
Chowdhury, Nadim
Palacios, Tomas
Date Issued
October 2017
Journal
2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)
Publisher
IEEE
Citation
Chowdhury, Nadim, and Tomas Palacios. “Nanostructured GaN Transistors.” 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Miami, FL, USA, 22-25 October 2017, IEEE, 2017, pp. 1–3.
Version
Author's final manuscript
Abstract
This paper describes how the use of nanostructures can significantly increase the performance of GaN transistors. 100-400 nm fins have been defined underneath the gate electrode of AlGaN/GaN transistors to increase the gate modulation efficiency of these devices and to allow for the tuning of the threshold voltage. The proper design of these fins allows not only an improvement in the DC performance of the device, but also a significant enhancement of the rf linearity of the transistors. The excellent electron transport in these nanostructures, combined with the wide bandgap of GaN, its large effective mass and its moderate electric permittivity, also allows the potential scaling of GaN transistors below 5 nm channel length. The theoretical performance of these ultra-scaled devices is benchmarked with respect to other competing technologies.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/csics.2017.8240466
