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Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation

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Author(s)
Babb, Jonathan William
Advisor(s)
Agarwal, Anant
Date Issued
November 1993
Series/Report no.
MIT-LCS-TR-586
Abstract
Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries.
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