Algorithms, architectures and circuits for low power HEVC codecs
Name
892647841-MIT.pdf
Description
Full printable version
Size
9.16 MB
Format
Adobe PDF
Checksum (MD5)
7c06aa49fc739245586719f9f2dd0216
Author(s)
Juvekar, Chiraag (Chiraag Shashikant)
Advisor(s)
Anantha P. Chandrakasan.
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
In order to satisfy the demand for high quality video streaming, aggressive compression is necessary. High Efficiency Video Coding (HEVC) is a new standard that has been designed with the goal of satisfying this need in the coming decade. For a given quality, of video HEVC offers 2x better compression than existing standards. However, this compression comes at the cost of a commensurate increase in complexity. Our work aims to control this complexity in the context of real-time hardware video codecs. Our work focused on two specific areas: Motion Compensation Bandwidth and Intra Estimation. HEVC uses larger filters for motion compensation leading to a significant increase in decoder bandwidth. We present a novel motion compensation cache that reduces external memory bandwidth by 67% and power by 40%. The use of large, variable-sized coding units and new prediction modes results in a dramatic increase in the search space of a video encoder. We present novel intra estimation algorithms that substantially reduce encoder complexity with a modest 6% increase in BD-rate. These algorithms are co-designed with the hardware architecture allowing us to implement them within reasonable hardware constraints.
Description
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
30
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 81-84).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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