SSTA design methodology for low voltage operation
Name
681914679-MIT.pdf
Description
Full printable version
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7.79 MB
Format
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Author(s)
Rithe, Rahul (Rahulkumar Jagdish)
Advisor(s)
Anantha P. Chandrakasan.
Alternative Title
Statistical static timing analysis design methodology for low voltage operation
Date Issued
2010
Publisher
Massachusetts Institute of Technology
Abstract
Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor parameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new kind of statistical variation, known as Local or Intra-die variation, has become important for logic and memory. Local variations are primarily the result of variations in the number of dopant atoms in the channel of CMOS transistors. To achieve ultra-low power, ICs are being designed for VDD
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Includes bibliographical references (p. [101]-103).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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