Fault Tolerance in Packet Communication Computer Archiectures
Name
MIT-LCS-TR-250.pdf
Size
6.47 MB
Format
Adobe PDF
Checksum (MD5)
8fe5377d515ba7779337557bd27d60a6
Author(s)
Leung, Clement Kin Cho
Advisor(s)
Dennis, Jack B.
Date Issued
December 1980
Series/Report no.
MIT-LCS-TR-250
Abstract
It is attractive to implement a large scale parallel processing system as a self-timed hardware system with decentralized control and to improve maintainability and availability in such a system through fault tolerance. In this thesis we show how to tolerate hardware failures in a self-timed hardware system with a packet communication architecture, designed to execute parallel programs organized by data flow concepts.
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