Energy-Aware Hardware Implementation of Network Coding
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chandrakasan_Energy-aware.pdf
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342.17 KB
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Author(s)
Angelopoulos, Georgios
Chandrakasan, Anantha P.
Medard, Muriel
Date Issued
May 2011
Journal
NETWORKING 2011 Workshops
Publisher
Springer-Verlag
Citation
Angelopoulos, Georgios, Muriel Medard, and Anantha P. Chandrakasan. “Energy-Aware Hardware Implementation of Network Coding.” Lecture Notes in Computer Science (2011): 137–144.
Version
Author's final manuscript
Abstract
In the last few years, Network Coding (NC) has been shown to provide several advantages, both in theory and in practice. However, its applicability to battery-operated systems under strict power constraints has not been proven yet, since most implementations are based on high-end CPUs and GPUs. This work represents the first effort to bridge NC theory with real-world, low-power applications. In this paper, we provide a detailed analysis on the energy consumption of NC, based on VLSI design measurements, and an approach for specifying optimal algorithmic parameters, such as field size, minimizing the required energy for both transmission and coding of data. Our custom, energy-aware NC accelerator proves the feasibility of incorporating NC into modern, low-power systems; the proposed architecture achieves a coding throughput of 80MB/s (60MB/s), while consuming 22uW (12.5mW) for the encoding (decoding) process.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1007/978-3-642-23041-7_14
