Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine
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Devadas_Design tradeoffs.pdf
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Author(s)
Shim, Keun Sup
Lis, Mieszko
Cho, Myong Hyon
Devadas, Srinivas
Lebedev, Ilia A.
Date Issued
October 2013
Journal
Proceedings of the 2013 IEEE 31st International Conference on Computer Design (ICCD)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Shim, Keun Sup, Mieszko Lis, Myong Hyon Cho, Ilia Lebedev, and Srinivas Devadas. “Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine.” 2013 IEEE 31st International Conference on Computer Design (ICCD) (n.d.).
Version
Author's final manuscript
Abstract
As transistor technology continues to scale, the architecture community has experienced exponential growth in design complexity and significantly increasing implementation and verification costs. Moreover, Moore's law has led to a ubiquitous trend of an increasing number of cores on a single chip. Often, these large-core-count chips provide a shared memory abstraction via directories and coherence protocols, which have become notoriously error-prone and difficult to verify because of subtle data races and state space explosion. Although a very simple hardware shared memory implementation can be achieved by simply not allowing ad-hoc data replication and relying on remote accesses for remotely cached data (i.e., requiring no directories or coherence protocols), such remote-access-based directoryless architectures cannot take advantage of any data locality, and therefore suffer in both performance and energy. Our recently taped-out 110-core shared-memory processor, the Execution Migration Machine (EM[superscript 2]), establishes a new design point. On the one hand, EM[superscript 2] supports shared memory but does not automatically replicate data, and thus preserves the simplicity of directoryless architectures. On the other hand, it significantly improves performance and energy over remote-access-only designs by exploiting data locality at remote cores via fast hardware-level thread migration. In this paper, we describe the design choices made in the EM[superscript 2] chip as well as our choice of design methodology, and discuss how they combine to achieve design simplicity and verification efficiency. Even though EM[superscript 2] is a fairly large design-110 cores using a total of 357 million transistors-the entire chip design and implementation process (RTL, verification, physical design, tapeout) took only 18 man-months.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1109/ICCD.2013.6657037
