Key receiver circuits for digital beamforming in millimeter-wave imaging
Name
727061426-MIT.pdf
Description
Full printable version
Size
19.73 MB
Format
Adobe PDF
Checksum (MD5)
2b6d76a994345bb11730284e5bd446f2
Author(s)
Nguyen, Khoa Minh
Advisor(s)
Charles G. Sodini.
Alternative Title
Key receiver circuits for digital beamforming in MMW imaging
Date Issued
2011
Publisher
Massachusetts Institute of Technology
Abstract
Millimeter-wave (MMW) frequencies have wavelengths small enough to offer sufficient spatial resolution for certain imaging applications. Advances in silicon processes have developed devices that can operate at these frequencies, which has led to the potential for low cost MMW imaging, provided that the circuit design can meet the performance specifications for these applications. In this research, we investigate key components for an active phased array imaging system operating at 77GHz that performs purely digital beamforming. Each element in the phased array has an antenna and processor that measures the phase and amplitude of the received signal. The focus of this thesis is the quality of the phase measurement. Phase noise from the receiver's front-end circuits will degrade the spatial resolution and image integrity. The system requires a MMW phase-locked loop (PLL) to generate the local oscillator. The PLL is a significant contributor to phase noise. A MMW PLL was designed in a 0.13tm silicon-germanium BiCMOS technology for low phase noise and power consumption while maintaining enough output power to robustly drive a mixer load. Measurement results show a de-embedded single-ended output power of -2dBm, a phase noise of -8ldBc/Hz at 1MHz offset corresponding to ips of timing jitter at the carrier, and a total power dissipation of 107mW. A new technique called digital phase tightening reduces phase noise from receiver front-end circuits to allow precise phase estimation for digital beamforming. This technique leverages the large ratio between the MMW carrier frequency and the low frame rates in imaging applications. By mixing down to an intermediate frequency (IF) and then averaging over many samples, we reduce phase error caused by phase noise. A test chip demonstrating the phase tightening concept was designed and characterized. We show that we can reduce RMS error from 450ps to 1.4ps at a 175MHz IF which corresponds to reducing ips of jitter to 3fs at a 77GHz carrier.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 123-129).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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