A 9GHz injection locked loop optical clock receiver in 32-nm CMOS
Name
711074216-MIT.pdf
Description
Full printable version
Size
6.53 MB
Format
Adobe PDF
Checksum (MD5)
f3210bb5778a3ef7aed11e6cdbb66615
Author(s)
Leu, Jonathan Chung
Advisor(s)
Vladimir Stojanović.
Alternative Title
Nine gigahertz injection locked loop optical clock receiver in 32-nm CMOS
Date Issued
2010
Publisher
Massachusetts Institute of Technology
Abstract
The bottleneck of multi-core processors performance will be the I/O, for both on-chip core-to-core I/0, and off-chip core-to-memory. Integrated silicon photonics can potentially provide high-bandwidth low-power signal and clock distribution for multicore processors, by exploiting wavelength-division multiplexing. This thesis presents the technology environment of the monolithic optical/electrical chip, and then focuses on how an optical method would look like for both source-synchronous link and for on-chip global clock distribution. The injection-locked loop clock receiver that suits this architecture breaks the bandwidth/sensitivity tradeoff, and a self-adjusting mechanism is added to increase robustness. The simulated receiver sensitivity is - 14dBm at 9GHz, consuming 77.14pW and generating jitter within 0. 15ps when locked onto a mode-locked laser clock source. The chip infrastructure and testing procedures are then presented, and lastly a truly integrated optical-electrical design flow is shown as well.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 65-68).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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