Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine
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Sinangil_ICIP_2012_architecture.pdf
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Author(s)
Sinangil, Mahmut E.
Chandrakasan, Anantha P.
Sze, Vivienne
Zhou, Minhua
Sinangil, Mahmut
Date Issued
September 2012
Journal
Proceedings of the 2012 19th IEEE International Conference on Image Processing (ICIP)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Sinangil, Mahmut E., Anantha P. Chandrakasan, Vivienne Sze, and Minhua Zhou. “Memory Cost Vs. Coding Efficiency Trade-Offs for HEVC Motion Estimation Engine.” 2012 19th IEEE International Conference on Image Processing (September 2012).
Version
Author's final manuscript
Abstract
This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ICIP.2012.6467164
