The design of an efficient hardware subroutine protocol for FPGAs
Name
31161980-MIT.pdf
Description
Full printable version
Size
2.84 MB
Format
Adobe PDF
Checksum (MD5)
7cd1886e0b6aad2527f4e57b36e548b2
Author(s)
Bauer, Trevor Joseph
Advisor(s)
Anant Agarwal.
Date Issued
1994
Publisher
Massachusetts Institute of Technology
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 54-55).
Subjects
Electrical Engineering and Computer Science
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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