Jigsaw: Scalable software-defined caches
Name
Sanchez_Jigsaw.pdf
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387.97 KB
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Adobe PDF
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Author(s)
Beckmann, Nathan Zachary
Sanchez, Daniel
Date Issued
September 2013
Journal
Proceedings of the 2013 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Beckmann, Nathan and Daniel Sanchez. "Jigsaw: Scalable software-defined caches." In 2013 22nd International Conference on Parallel Architectures and Compilation Techniques, 7-11 Sept. 2013, Edinburgh, Scotland. IEEE, p.213-224.
Version
Author's final manuscript
Abstract
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunately, prior research addressing one issue either ignores or worsens the other: NUCA techniques reduce access latency but are prone to hotspots and interference, and cache partitioning techniques only provide isolation but do not reduce access latency.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/PACT.2013.6618818
