High-level automatic pipelining for sequential circuits
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isss01.pdf
Description
Accepted version
Size
92.84 KB
Format
Adobe PDF
Checksum (MD5)
595f36fdb7d2df764072ca7354ce0648
Author(s)
Marinescu, Maria-Cristina V
Rinard, Martin
Date Issued
2001
Journal
Proceedings of the 14th international symposium on Systems synthesis - ISSS '01
Publisher
ACM Press
Citation
Marinescu, Maria-Cristina V and Rinard, Martin. 2001. "High-level automatic pipelining for sequential circuits." Proceedings of the 14th international symposium on Systems synthesis - ISSS '01.
Version
Author's final manuscript
Abstract
This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation. We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1145/500001.500053
