Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications
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Author(s)
Kim, Dae-Hyun
del Alamo, Jesus A.
Date Issued
June 2010
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Kim, Dae-Hyun, and Jesús A. del Alamo. “Scalability of Sub-100 Nm InAs HEMTs on InP Substrate for Future Logic Applications.” IEEE Transactions on Electron Devices 57.7 (2010). © Copyright 2012 IEEE
Version
Final published version
Abstract
We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subchannel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as I[subscript ON]/I[subscript OFF] = 9 × 10[superscript 4], drain-induced-barrier lowering = 80 mV/V, S = 70 mV/dec, and an estimated logic gate delay of 0.6 ps at V[subscript DS] = 0.5 V. In addition, we have obtained excellent high-frequency operation with L[subscript g] = 40 nm, such as f[subscript T] = 491 GHz and f[subscript max] = 402 GHz at V[subscript DS] = 0.5 V. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit I[subscript ON] = 0.6 A/μm at I[subscript Leak] = 200 nA/μm. This is about two times higher I[subscript ON] than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and I[subscript Leak].
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1109/ted.2010.2049075
